Voltage Controlled Delay Line with Phase Quadrature Outputs for [0.9-4]GHz Factorial Delay Locked Loop Dedicated to Zero-IF Multi-Standard Local Oscillator

Nowadays, RF communication standards for voice and data are widely being developed, particularly in the [1-4] GHz band (GSM, DCS, UMTS, Wi-Fi, Bluetooth, WiMax...). Strict requirements are linked with each application, and as a consequence, constraints are growing for communication terminals. Moreover, according to low-cost and low-power considerations, a RF transmitter should be able to deal with all of the existing standards. In this way, terminals should be completely reconfigurable. Software Defined Radio [1] is the best solution to achieve such a concept, but this kind of architecture is not yet available. Indeed, in such a system, the Analog to Digital Converter (ADC) and the Digital to Analog Converter (DAC) are located just after/before the antenna. But such a solution needs converter data rate to be in the order of 2 GBit/s with 16 bits resolution which is not yet suitable with wireless system low power constraints [2]. An intermediate solution is to use reconfigurable blocks in RF terminals [3]. The most appropriated RX-TX architecture to this latter solution is the zero-IF one. Indeed, it offers advantages in terms of integration and power consumption reduction compared to heterodyne and low IF one. This paper focuses on one of the most critical block of the chain: the local oscillator (LO). In a RF transmission chain, the role of the LO is to provide the high frequency signal to the mixer. So, its characteristics can really impact in the overall expected performances of the chain. Traditionally, a LO is built using a frequency synthesizer. When designing a frequency synthesizer, several requirements have to be carefully respected which are mainly the output frequency and the phase noise. Table I provides the expected specifications of several standards [4] in the targeted band. As one can notice, specifications depend on the standard and are different one from the others. So, to act at multi-standard, it becomes necessary that the LO output frequency range achieves a 3GHz bandwidth. To respect the phase noise requirements, it should agree with the mask defined by the lowest phase noise that is to say -110dBc/Hz at 200kHz and -129dBc/Hz at 5MHz. Finally, it may provide two outputs in quadrature phase in order to be zero-IF architecture compliant. Usually, frequency synthesizers are built around Phase Locked Loop (PLL). Unfortunately, this last architecture offers such a large output frequency range only at the price of very poor close-in phase noise. Recently, a new architecture has shown its ability to fulfill multi-standard LO requirements: the Factorial Delay Locked Loop (F-DLL) [5]. ABSTRACT1